1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for forming interconnect lines with improved use of low k dielectric material in the intermetal dielectric material electrically separating such interconnect lines.
2. Description of the Related Art
An integrated circuit includes numerous active devices arranged on a single substrate. In order to implement desired functions, select components of a circuit must be interconnected. Interconnects, or thin lines of conductive material, are used to form electrical connections between active devices. In the desire to build more complex integrated circuits, the active device density within a given chip has greatly increased. Because of space limitations caused in large part by the increase in active device density, multiple levels of interconnect must often be used. Within each level of interconnect, interconnect lines are insulated from underlying levels, overlying levels, and each other by dielectric materials.
The performance of an integrated circuit is limited by its propagation delay, notably known as the time required for a signal to travel from one point within the circuit to another. As the feature size decreases, the need to reduce the resistance and capacitance, and thus the RC delay, associated with interconnection paths becomes more urgent. For example, in submicron metal oxide semiconductor field-effect transistors (MOSFETs) the interconnect RC delay can exceed delays due to gate switching. In order to continue to improve integrated circuit performance, these RC delays must be decreased.
There are numerous factors that effect the RC delay of interconnect lines. One of these factors is the resistance, R, of the interconnect lines, which may be defined as:
R=(xcfx81L)/WLTC
where xcfx81 represents resistivity of the conductive material, L is the interconnect length, WL is the interconnect width, and TC is the interconnect thickness. Obviously, if low resistivity materials are used as interconnect, signals will be able to propagate through the circuit faster. Consequently, metals such as aluminum and copper are often used to form interconnect lines. Although increasing the width and thickness of interconnect lines will also help to decrease the resistivity of such lines, increases in line dimensions are limited by the available space and the fact that the capacitance between lines increases as the spacing between lines decreases.
Interconnect RC delay is also affected by the parasitic capacitances between laterally spaced conductors (i.e., intralevel capacitance) and between vertically spaced conductors or between a conductor and the underlying substrate (i.e., interlevel capacitance). Increases in active device density may cause the dielectric spacing between levels of interconnect and within levels of interconnect to decrease. As the dielectric spacing between levels of interconnect decreases, the interlevel capacitance must conversely increase. Likewise, as the dielectric spacing within a level of interconnect decreases, the intralevel capacitance increases. Unfortunately, increases in these parasitic capacitances may result in lengthening of the propagation delay.
Interlevel and intralevel capacitances may be reduced, however, by reducing the permittivity, ∈, of the intermetal dielectric material used to separate conductors. By normalizing the permittivity, ∈, of a material to the permittivity of vacuum, ∈o, the relative permittivity of a material can be determined. Relative permittivity, or dielectric constant, k, is typically used in place of permittivity. The dielectric constant of a material is defined as:
xe2x80x83k=∈/∈o
The k value of the dielectric material used to insulate interconnect lines has a strong effect on the intermetal capacitance, C, which may be defined as follows:
C=k∈oWLTC/Td
where Td is the thickness of the dielectric material between adjacent interconnect lines. Not only will low k dielectric materials (i.e., those materials that have k values less than about 3.5) reduce intermetal parasitic capacitances, but many, such as low k spin-on glasses (xe2x80x9cSOGsxe2x80x9d) may be used to fill narrower spaces without causing voids often encountered in conventional chemical vapor deposited (xe2x80x9cCVDxe2x80x9d) films. Common SOG materials include silicates or siloxanes mixed in alcohol-based solvents.
Because of the aforementioned properties, SOGs are often used as intermetal dielectrics. A conventional process that incorporates SOG in this manner is the etchback SOG process. One unfortunate characteristic of SOGs (and many other low k dielectric materials) is that they have a low density, and thus tend to absorb moisture easily. If contacts are formed through SOG, moisture from the SOG may migrate into the vias, potentially causing the undesirable xe2x80x9cpoisoned viaxe2x80x9d effect. An advantage of the etchback SOG process is that SOG is removed from raised areas where contacts may be formed.
In this process, a first interlevel dielectric film is CVD deposited over a set of patterned metal interconnect and serves as a liner between the metal and any dielectric material deposited in the gaps between adjacent interconnect. This film, usually a CVD silicon oxide (xe2x80x9coxidexe2x80x9d), will generally conform to the interconnect topography. As a result, the spaces between adjacent interconnect will be more narrow than before the interlevel dielectric was deposited. A SOG film is then spun on, and fills the remainder of the gap between the interconnects. Portions of the SOG layer and the uppermost layer of the first CVD dielectric layer are then removed, typically using a dry plasma etch process. In this manner, SOG material is removed in areas where vias will be etched and contacts formed, but remains in the gaps between interconnect. A second oxide interlevel dielectric film is then deposited.
One problem of the etchback SOG process is that the first interlevel dielectric must be deposited at a thickness sufficient to prevent the underlying metal interconnects from being exposed during the etchback step. Because this film is deposited at this thickness over the entire interconnect topography, the amount of space available between adjacent interconnect for low k dielectric material may be reduced. If the interlevel dielectric layer becomes too thick, the spacing may even be reduced to the point where SOG cannot sufficiently flow between the coated interconnect. As the spacing between adjacent interconnects grows smaller, this xe2x80x9cpinching offxe2x80x9d effect only increases.
In addition, there is typically a substantial difference in the etch rate between the SOG in the gap fill and the oxide in the interlevel dielectric layer. As a result, the topography defined by the interlevel dielectric film and the SOG gap fill may not be sufficiently planar. An insufficient degree of non-planarization can hinder the reliable manufacture of overlying interconnects. The need for an increased degree of planarization becomes even greater as the interconnect pitch (i.e., the sum of the interconnect line width and the space between the adjacent interconnect lines) decreases. Furthermore, the etch chemistry of many low dielectric constant materials closely resembles that of photoresist, which makes them very difficult to etch. Consequently, it is troublesome to incorporate such materials into process flows that incorporate etchback techniques in a manner similar to the SOG etchback process.
Therefore, it would be desirable to develop a technique for fabricating interconnect in which the amount of low k dielectric material utilized could be increased. It would also be advantageous to increase the degree of planarization of the intermetal dielectric topography. The improved process would allow the use of difficult-to-etch, low k value dielectric materials.
The problems identified above are in large part solved by the method presented herein for forming interconnect lines with improved use of low k dielectric material in the intermetal dielectric material insulating such interconnect lines. In this method, a metal layer and a dielectric layer arranged upon the metal layer may both be patterned to form interconnect structures that each include an interlevel dielectric portion and metal interconnect portion. A liner may then be deposited upon the interconnect structures and the semiconductor substrate. The interconnect structures are spaced by gaps, which may then be filled by a low k dielectric material. The low k dielectric material may then be planarized.
Unlike the SOG etchback process, the present method allows for formation of interlevel dielectric portions exclusively above the metal interconnect portions of the interconnect structures. Since the interlevel dielectric portions may be contained above the metal interconnect portions, the desire to form a thick layer of a dielectric material (e.g., oxide) directly above the metal interconnects does not reduce the space available between adjacent interconnect structures for low k dielectric material. Consequently, the liner, which is formed over the interconnect structures, does not need to function to prevent erosion of the metal interconnect portions during planarization. The liner, therefore, may be deposited thinner than the interlevel dielectric layer of the SOG etchback process. The thinner liner creates more space between the interconnect structures, and allows a greater quantity of low k dielectric material to utilized therebetween.
Furthermore, any contacts made to the metal interconnect portions of the interconnect structures are preferably made through the interconnect structures"" interlevel dielectric portions and not through the low k dielectric material disposed between the interconnect structures. Thus, low k materials may be used that, because of their difficulty of etching, would not be available if it was necessary to etch a via in the low k dielectric material to form the contact. It should also be noted that formation of the liner is not strictly necessary. If the low k dielectric material is compatible with the metal interconnect portions and the critical dimensions of any contacts made to the metal interconnect portions are narrow, then the liner may not be necessary. Additionally, if the metal used for the contacts is compatible with the low k dielectric material, then the liner again may not be needed.
Planarization of the low k dielectric material is preferably undertaken by chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d). The use of polishing techniques instead of etchback techniques to planarize the low k material may allow the use of difficult-to-etch materials, such as many low dielectric constant polymers. In addition, polish stop portions arranged above the interlevel dielectric portions of the interconnect structures may be used to increase polish uniformity. Use of the present method preferably results in an interconnect level that exhibits a high degree of planarization.
According to one embodiment, a liner is formed upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical-mechanical polishing. Planarization of the low k dielectric material is preferably discontinued before a substantial amount of the interlevel dielectric portions of the interconnect structures is removed.
In addition, a polish stop portion may be arranged upon the interlevel dielectric portion of each interconnect structure. The polish stop portion is preferably composed of silicon nitride. Polishing of the low k material is discontinued at a point in time subsequent to the initiation of polishing of the polish stop portions. Because the polish stop portions are preferably highly resistant to abrasive removal, polishing of the low k material may be extended for a time sufficient to produce a high degree of planarization. After polishing is completed, the polish stop portions may be removed using, e.g., etchback.
Alternately, the liner may be composed of a material (e.g., silicon nitride) that is configured to serve as a polish stop. Because many of the materials used as polish stops have relatively high k values, the overall k value of the aggregate intermetal dielectric (i.e., the composite of the dielectric constants of the low k gap fills, the liner, and the interlevel dielectric portions) may increase. However, using the liner as a polish stop allows the benefits of increased planarity without adding additional process steps, which may make this process flow a viable alternative.
According to another embodiment, a layer of metal is first formed upon a semiconductor topography. A layer of dielectric material may be formed upon the layer of metal. These layers may be patterned to form spaced interconnect structures, with gaps defined between adjacent interconnect structures. Each interconnect structure preferably includes an interlevel dielectric portion arranged upon a metal interconnect portion. In patterning the layer of dielectric material, resist may be spun on, exposed, and developed as is well known in the art to provide the patterned masking layer used to define the interconnect structures during subsequent etching steps. As an alternate process flow, the masking layer may be removed after etching the layer of dielectric material, and the patterned interlevel dielectric layer may be used as a hard mask for etching the metal. In addition, a polish stop layer may be formed above the layer of dielectric material. After etching of the polish stop layer and the layer of dielectric material, the masking layer used to define the pattern for these may be removed. Then, the patterned polish stop layer and the patterned interlevel dielectric layer may be used as a hard mask.
A liner may be subsequently formed upon the semiconductor topography, preferably by deposition of silicon dioxide. A low k dielectric material may then be deposited over the interconnect structures such that the low k dielectric material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may be any of a variety of dielectric materials having a k value of less than about 3.5. These materials may include fluorine-doped silicon oxide, spin-on glasses, and polymers. The manner of deposition is, of course, dependent on the material to be deposited. For example, the low k dielectric material can be spun-on or deposited using a plasma or non-plasma source. After deposition, the low k dielectric material may then be planarized.
In another embodiment, an integrated circuit is presented that includes a plurality of spaced interconnect structures arranged above a semiconductor topography. The interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion. A liner may be formed upon the plurality of interconnect structures and the semiconductor topography. A low k dielectric material substantially fills the gaps between adjacent interconnect structures. In addition, each of the interconnect structures may also include a polish stop portion arranged upon its interlevel dielectric portion. Alternately, the liner may be configured to serve as a polish stop.